It is known that EEPROM and Flash EEPROM memory devices can be programmed in one or another of two logical states by respectively introducing electrons into or removing electrons from the memory cells' floating gates. This latter operation is termed "writing" in EEPROMs, while in Flash EEPROMs, it is referred to as "erasure".
The removal of electrons from a cell's floating gate is accomplished by tunnelling electrons from the floating gate into an underlying N+ diffusion, which in the case of a Flash EEPROM device constitutes the source region of the cell, and in an EEPROM device can represent either the source or the drain region of the cell, through a thin oxide region called "tunnel oxide"; electron tunnelling takes place if the potential difference between the floating gate and said underlying diffusion is made negative and its absolute value exceeds a value depending on the cells' characteristics.
A common technique provides for grounding the cell's control gate (which is capacitively coupled to the floating gate), while raising the underlying diffusion potential to a value generally higher than 10 V.
When, however, the diffusion potential is raised to such values, band-to-band tunnelling causes significant leakage currents to appear, thereby making it impossible to program the memory device by just supplying it one single voltage supply, or to use the memory device in a battery-supplied environment.
To overcome such a problem, a different technique has been introduced, which provides for lowering the control gate potential to a negative value (with respect to the ground reference voltage) ranging from -6 V to -8 V and generated by a circuitry internal to the memory device, and raising the potential of the N+ diffusion under the tunnel oxide to a moderately high value, for example corresponding to the voltage supply value of the memory device.
A circuit implementing this technique is described in U.S. Pat. No. 5,077,691, and comprises three P-channel MOSFETs, two of which are connected in series between the output of a positive high voltage (Vpp) source and an N-channel MOSFET having a source connected to ground, while the third is connected between the common node of the previous two MOSFETs and the output of a negative high voltage (Vnn) source; the common node to which the three MOSFETs are connected represents a control gate line or word line that is connected to the control gates of the cells to be programmed; the Vpp and Vnn sources are constituted by charge pumps or voltage boosters internal to the memory device, and generally located at the periphery of the chip.
To transfer electrons to the floating gates of the cells to be programmed, the charge pump for generating Vpp is activated, and the MOSFET connected between Vpp and the control gate line is on; the remaining two MOSFETs are instead kept off, and the charge pump for generating Vnn is deactivated. It is thus possible to transfer the voltage Vpp to the control gate line.
To remove electrons from the floating gates of the cells to be programmed, the charge pump generating Vnn is activated, the two serially-connected MOSFET are kept off, and the third MOSFET is on, so that Vnn can be transferred to the control gate line. The voltage effectively transferred to the control gate line is actually given by the voltage applied to the gate of the third MOSFET minus the MOSFET threshold voltage (which is negative since P-channel MOSFETs are used); the gate voltage of the third MOSFET is never equal to Vnn, since voltage drops always occur between the output of the Vnn charge pump and the gate of the third MOSFET, due to the long interconnection line and the presence of selection transistors. The gate voltage of the third MOSFET is, therefore, in an absolute value sense, lower than Vnn.
Because the third MOSFET has its source connected to the control gate line and the body (i.e., the N well in which the P-channel MOSFETs are obtained) connected to ground, the MOSFET threshold voltage increases (in absolute value) and the voltage effectively transferred to the control gate line can be 2 or 3 V higher than the voltage applied to the gate of the MOSFET. This value could be not sufficiently negative to start tunnelling of electrons.
A possible solution to the above-mentioned problem provides for voltage boosting the gate of the third MOSFET, at the expense of an increase in both the complexity of the circuit and in the total memory-chip area.